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[Other resource] vga.niosII.compent.v

Description: 在cyloneIIFPGA平台下设计完成测试通过的VGA控制器代码。显存留在系统的SDRAM中，用FIFO作为缓冲。-in cyloneIIFPGA platform design is completed tests through the VGA controller code. RAM in the system SDRAM, and use as a FIFO buffer.
Platform: | Size: 6599 | Author: Ray ZH | Hits:

[Other resource] leon3-altera-ep2s60-ddr

Description: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Platform: | Size: 114780 | Author: king.xia | Hits:

[VHDL-FPGA-Verilog] sdramcore

Description:
Platform: | Size: 19456 | Author: 韩 | Hits:

[VHDL-FPGA-Verilog] leon3-altera-ep2s60-ddr

Description: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Platform: | Size: 114688 | Author: | Hits:

[Software Engineering] SDRAM

Description: 连接Nios II 和SDRAM的系统设计，DDR SDRAM设计及调试经验总结，MT48LC16M16资料。-failed to translate
Platform: | Size: 1903616 | Author: luyi | Hits:

[VHDL-FPGA-Verilog] image_control

Description: NIOSII通过IP核读取CMOS图像传感器在SDRAM中的数据-NIOSII read through the IP core in CMOS image sensor data in SDRAM
Platform: | Size: 1024 | Author: 尹长生 | Hits:

[VHDL-FPGA-Verilog] EP2C8_SDRAM_FLASH

Description: NIOSII FLASH设置程序范例，sopc应用-NIOSII FLASH setup example, sopc application
Platform: | Size: 6361088 | Author: liming | Hits:

[VHDL-FPGA-Verilog] mysopc

Description: 基于友晶DE0开发板做的NiosII最小系统，主要是修正了开发板上闪存连线错误，已经测试过，烧到DE0里面就直接可以跑了。SDRAM和FLASH存储器都可以正常运行，里面还有一个用于点亮LED的小程序，是用软核实现的，从而证明该最小系统可以正常运行，其余的扩展可以自行开发-Friends of grain-based development board to do NiosII DE0 minimum system, mainly Fixed connection error on the development board flash memory has been tested, SDRAM and FLASH memory can be normal operation, there is also a small program for LED lighting, soft-core implementation is to prove that the minimum system functions properly, the rest of the extensions can be developed
Platform: | Size: 17147904 | Author: 周磊 | Hits:

[VHDL-FPGA-Verilog] fpga-display-bmp-pictures

Description: 本文设计的是基于大规模FPGA的BMP图库管理，完成了数码相框的一部分功能。并且本文详细地介绍了BMP图库管理的软硬件实现，即采用Altera的CyclonII系列EP2C20F484C7作为主控芯片，内嵌32位的NiosII软核，采用SDRAM作为内存，把存储在SD卡内的二进制图片信息读入内存，并控制TFT彩色液晶，读取图片数据送到液晶上显示。整个过程的所有设备都是通过Avalon总线挂在NiosII上，在NiosII的协调下正常工作。 本作品最终能显示存入SD卡内的彩色图片信息，图片显示很流畅，没有延时。并且能通过4个按键分别完成图片的上翻、下翻、放大和缩小。-This design is based on the large-scale FPGA-BMP library management, and completed part of the features of digital photo frame. This paper describes the library management software and hardware to achieve BMP photos, that used the Altera s CyclonII series EP2C20F484C7 as the master chip, embedded soft-core 32-bit NiosII, the use of SDRAM for memory, SD card stored the binary picture information read into memory, and control TFT color LCD, read the image form the memory data to the LCD display. All equipment of the process hanging in the NiosII through Avalon bus, with the NiosII CPU and complete the coordination of work. Eventually the work can show the color pictures of information stored into the SD card, pictures show smoothly, and with no delay. And with 4 keys, respectively, we can make the TFT display the previous image or the next image,and make the pictures zoom in or zoom out.
Platform: | Size: 2168832 | Author: wuwei | Hits:

[VHDL-FPGA-Verilog] DE1_fat32

Description: 本文设计的是基于大规模FPGA的BMP图库管理，完成了数码相框的一部分功能。并且本文详细地介绍了BMP图库管理的软硬件实现，即采用Altera的CyclonII系列EP2C20F484C7作为主控芯片，内嵌32位的NiosII软核，采用SDRAM作为内存，把存储在SD卡内的二进制图片信息读入内存，并控制TFT彩色液晶，读取图片数据送到液晶上显示。整个过程的所有设备都是通过Avalon总线挂在NiosII上，在NiosII的协调下正常工作。 本作品最终能显示存入SD卡内的彩色图片信息，图片显示很流畅，没有延时。并且能通过4个按键分别完成图片的上翻、下翻、放大和缩小。-This design is based on the large-scale FPGA-BMP library management, and completed part of the features of digital photo frame. This paper describes the library management software and hardware to achieve BMP photos, that used the Altera s CyclonII series EP2C20F484C7 as the master chip, embedded soft-core 32-bit NiosII, the use of SDRAM for memory, SD card stored the binary picture information read into memory, and control TFT color LCD, read the image form the memory data to the LCD display. All equipment of the process hanging in the NiosII through Avalon bus, with the NiosII CPU and complete the coordination of work. Eventually the work can show the color pictures of information stored into the SD card, pictures show smoothly, and with no delay. And with 4 keys, respectively, we can make the TFT display the previous image or the next image,and make the pictures zoom in or zoom out.
Platform: | Size: 11721728 | Author: wuwei | Hits:

[VHDL-FPGA-Verilog] DE2_70_NIOS_10_flash

Description: 首先将此Verilog程序下载到DE2-70开发板上后，然后用NiosII软件将任何文件的二进制数据写入到ssram或者sdram等存储器重去，并可以指定起始地址。-First program this Verilog downloaded to the DE2-70 development board, and then the use NiosII software binary data of any file written to memory such as ssram or sdram weight go, and you can specify a starting address.
Platform: | Size: 1620992 | Author: boyzone | Hits:

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